1. Field of the Invention
The present invention relates to a field programmable gate array (FPGA) architecture. More particularly, the present invention relates to the routing resources within a logic block for increasing the routing flexibility in an FPGA architecture.
2. Background
In the FPGA art, both antifuse based programmable architectures and SRAM based reprogrammable architectures are well known. In an FPGA, the logic elements in the gate array are connected together by routing resources to form a desired integrated circuit. The routing resources are connected to each other and to the logic elements in the gate array by programmable elements. In an antifuse based device, the number of the programmable elements far exceeds the number of elements in an SRAM based device because the area required for an antifuse is much smaller than an SRAM bit. Despite this space disadvantage of an SRAM based device, SRAM based devices are implemented because they are reprogrammable, whereas an antifuse device is presently one-time programmable.
Due to the area required for an SRAM bit, a reprogrammable SRAM bit cannot be provided to connect routing resources to each other and the logic elements at every desired location. The selection of only a limited number of locations for connecting the routing resources with one another and the logic elements is termed “depopulation”. Because the capability to place and route a wide variety of circuits in an FPGA depends upon the availability of routing and logic resources, the selection of the locations at which the programmable elements should be made with great care.
Some of the difficulties faced in the place and route caused by depopulation may be alleviated by creating symmetries in the FPGA. For example, look-up tables (LUT) are often employed at the logic level in an SRAM based FPGA, because a LUT has perfect symmetry among its inputs. The need for greater symmetry in a reprogrammable FPGA architecture does not end with the use of look-up tables. It also extends to the manner in which routing resources are connected together and the manner it which routing resources are connected to the logic elements. Without a high degree of symmetry in the architecture, the SRAM memory bit depopulation makes the place and route of nets in an SRAM based FPGA difficult.
As FPGAs have grown in size and complexity, the logic elements have typically been grouped into blocks which contain multiple combinatorial and sequential logic blocks that share interconnection and have local interconnect conductors for use inside the block. In these blocks, the inputs and outputs to the blocks are typically accessible to the general routing resources of the FPGA from at least two sides of the block, and sometimes from all four sides of the block.
Some inputs and outputs are accessible from more than one side of the block. An input or output that is accessible from more than one side of the block can provide a greater degree of flexibility for placing and routing the FPGA. For this reason, despite the fact that providing an input or output that is accessible from more than one side of the block requires additional silicon area, this feature is quite desirable. Typically, the routing conductors that provide access from two sides are pairwise shorted to essentially provide 2N access ports for each of the N shorted interconnect conductors. Although this increases flexibility, it is also wasteful, because in the majority of cases a connection to the general routing resources is made in a horizontal or vertical direction, but not both.
It is therefore an object of the present invention to provide the flexibility achieved by the routing conductors that provide access from two sides which are pairwise shorted, but eliminates the waste and also provide additional flexibility.